Publication detail

Compact Library of Efficient Polymorphic Gates based on Ambipolar Transistors

NEVORAL, J. ŠIMEK, V. RŮŽIČKA, R.

Original Title

Compact Library of Efficient Polymorphic Gates based on Ambipolar Transistors

Type

conference paper

Language

English

Original Abstract

Main goal of this paper is to propose a compact library of polymorphic gates based on suitable type of reconfigurable transistors. In fact, their exploitation brings a significant advantage for space-efficient synthesis of complex polymorphic circuits. Actual behaviour of those transistors closely depends on so called ambipolar property. That particular aspect simply allows the selection of n- or p- channel operating mode of the transistor structures which is controlled by means of switching the voltage level at a dedicated control electrode. The gates were developed by an evolution approach using Cartesian genetic programming. Various discrete switch-level ambipolar transistor models extended by taking into account the threshold voltage drop degradation effect were used. A diverse range of polymorphic gates were designed, which clearly shows significant transistor savings compared to the conventional approaches. Finally, the individual components that belong to the library also suggest the opportunity how to considerably reduce the target size of complex polymorphic circuits.

Keywords

Polymorphic gate, ambipolar transistor, digital circuit, Polymorphic electronics, HSPICE simulation.

Authors

NEVORAL, J.; ŠIMEK, V.; RŮŽIČKA, R.

Released

4. 4. 2017

Publisher

IEEE Circuits and Systems Society

Location

Palma de Mallorca

ISBN

978-1-5090-6376-5

Book

2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)

Pages from

155

Pages to

160

Pages count

6

BibTex

@inproceedings{BUT134717,
  author="Jan {Nevoral} and Václav {Šimek} and Richard {Růžička}",
  title="Compact Library of Efficient Polymorphic Gates based on Ambipolar Transistors",
  booktitle="2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)",
  year="2017",
  pages="155--160",
  publisher="IEEE Circuits and Systems Society",
  address="Palma de Mallorca",
  doi="10.1109/DTIS.2017.7930180",
  isbn="978-1-5090-6376-5"
}