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ŠŤASTNÝ, L.; MEGO, R.; FRANEK, L.; BRADÁČ, Z.
Original Title
Zero Cross Detection Using Phase Locked Loop
English Title
Type
Paper in proceedings (conference paper)
Original Abstract
This paper discusses zero cross detection method for the time synchronization purpose that is based on phase locked loop. After familiarizing with PLL concept and its blocks, example design of the PLL is realized. Simulation schema is introduced to examine and analyse PLL behaviour under different grid interferences. Performed tests show two potential issues multiple zero crossing in the zero cross area may cause instability of the loop and the presence of harmonics may cause shifts of the zero cross event.
English abstract
Keywords
zero crossings, detection algorithms, phase-locked loop, grid interferences
Key words in English
Authors
RIV year
2017
Released
05.10.2016
Location
Brno/Lednice
Book
14th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2016
ISBN
2405-8963
Periodical
IFAC-PapersOnLine
Volume
2016
Number
14
State
United Kingdom of Great Britain and Northern Ireland
Pages from
464
Pages to
468
Pages count
5
BibTex
@inproceedings{BUT128785, author="Ladislav {Šťastný} and Roman {Mego} and Lešek {Franek} and Zdeněk {Bradáč}", title="Zero Cross Detection Using Phase Locked Loop", booktitle="14th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2016", year="2016", journal="IFAC-PapersOnLine", volume="2016", number="14", pages="464--468", address="Brno/Lednice", doi="10.1016/j.ifacol.2016.12.050", issn="2405-8971" }