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SMÉKAL, D.; FROLKA, J.; HAJNÝ, J.
Original Title
Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays
English Title
Type
WoS Article
Original Abstract
This article deals with encryption on Field Programmable Gate Array (FPGA). The first part describes current state of symmetric and asymmetric cryptography. The following part focuses on the AES algorithm and its implementation in VHDL language. The last part shows testing results of mentioned implementation on card NFB-40G2 containing FPGA from Xilinx series Virtex-7.
English abstract
Keywords
AES, FPGA, VHDL, implementation, encryption, decryption, AddRoundKey, SubBytes, ShiftRows, MixColumns, NetCOPE
Key words in English
Authors
RIV year
2017
Released
05.10.2016
Publisher
IFAC-PapersOnLine
Book
14th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2016
ISBN
2405-8963
Periodical
Volume
49
Number
25
State
United Kingdom of Great Britain and Northern Ireland
Pages from
384
Pages to
389
Pages count
6
URL
http://www.sciencedirect.com/science/article/pii/S2405896316327136
BibTex
@article{BUT127756, author="David {Smékal} and Jakub {Frolka} and Jan {Hajný}", title="Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays", journal="IFAC-PapersOnLine", year="2016", volume="49", number="25", pages="384--389", doi="10.1016/j.ifacol.2016.12.075", issn="2405-8971", url="http://www.sciencedirect.com/science/article/pii/S2405896316327136" }