Publication result detail

Software Fault Tolerance: the Evaluation by Functional Verification

ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.

Original Title

Software Fault Tolerance: the Evaluation by Functional Verification

English Title

Software Fault Tolerance: the Evaluation by Functional Verification

Type

Paper in proceedings (conference paper)

Original Abstract

The aim of this paper is to present a new approach in evaluating Software Fault Tolerance (SFT) methodologies. It is the way on how to ensure fault tolerance without any additional hardware as is common in frequently used Triple Modular Redundancy (TMR). As our research is focused on electromechanical systems which are commonly driven by processors or Multi Processors Systems on Chip (MPSoC) we decided to use the soft-core processor running on Field Programmable Gate Array (FPGA) as our experimental platform. The new approach uses Functional Verification for automation of the evaluation process. The functional verification environment is one of the important parts of the presented evaluation platform architecture. Programs generation for a processor, where SFT is applied, is also important. Experiments with the programs generator and fault injection are presented and goals for future work are identified on that basis.

English abstract

The aim of this paper is to present a new approach in evaluating Software Fault Tolerance (SFT) methodologies. It is the way on how to ensure fault tolerance without any additional hardware as is common in frequently used Triple Modular Redundancy (TMR). As our research is focused on electromechanical systems which are commonly driven by processors or Multi Processors Systems on Chip (MPSoC) we decided to use the soft-core processor running on Field Programmable Gate Array (FPGA) as our experimental platform. The new approach uses Functional Verification for automation of the evaluation process. The functional verification environment is one of the important parts of the presented evaluation platform architecture. Programs generation for a processor, where SFT is applied, is also important. Experiments with the programs generator and fault injection are presented and goals for future work are identified on that basis.

Keywords

Software Fault Tolerance
SFT
Processor
Fault Injection
Electro-mechanical Systems
Functional Verification

Key words in English

Software Fault Tolerance
SFT
Processor
Fault Injection
Electro-mechanical Systems
Functional Verification

Authors

ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.

RIV year

2016

Released

26.08.2015

Publisher

IEEE Computer Society

Location

Funchal

ISBN

978-1-4673-8035-5

Book

Proceedings of the 18th Euromicro Conference on Digital Systems Design

Pages from

284

Pages to

287

Pages count

4

URL

https://ieeexplore.ieee.org/document/7302285

BibTex

@inproceedings{BUT119910,
  author="Ondřej {Čekan} and Jakub {Podivínský} and Zdeněk {Kotásek}",
  title="Software Fault Tolerance: the Evaluation by Functional Verification",
  booktitle="Proceedings of the 18th Euromicro Conference on Digital Systems Design",
  year="2015",
  pages="284--287",
  publisher="IEEE Computer Society",
  address="Funchal",
  doi="10.1109/DSD.2015.107",
  isbn="978-1-4673-8035-5",
  url="https://ieeexplore.ieee.org/document/7302285"
}