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BIOLEK, D.; BIOLKOVÁ, V.; KOLKA, Z.
Original Title
Memristor model for simulating large circuits for massively-parallel analog computing
English Title
Type
Paper in proceedings (conference paper)
Original Abstract
The model of memristor described in the paper is designed for building models of large networks for analog computations. A circuit containing thousands of memristors for finding the shortest path in a complicated maze is a typical example. The model is designed to meet the following criteria: 1. It is a model of HP memristor with linear dopant drift while respecting the physical bounds of the internal state variable. 2. Reliable operation in the SPICE environment also when simulating extremely large networks. 3. Minimization of the simulation time while computing bias points and during transient analyses. A benchmark circuit for testing the applications of various complexities is presented. The results confirm a perfect operation of the model also in applications containing thousands of memristors.
English abstract
Keywords
memristor; model; massively-parallel analog computations; SPICE
Key words in English
Authors
RIV year
2016
Released
14.10.2015
Publisher
AOS L. Mikuláš
Location
L. Mikuláš, Slovensko
ISBN
978-1-61804-245-3
Book
Proceedings of the KIT 2015
Pages from
1
Pages to
6
Pages count
BibTex
@inproceedings{BUT118256, author="Dalibor {Biolek} and Viera {Biolková} and Zdeněk {Kolka}", title="Memristor model for simulating large circuits for massively-parallel analog computing", booktitle="Proceedings of the KIT 2015", year="2015", pages="1--6", publisher="AOS L. Mikuláš", address="L. Mikuláš, Slovensko", isbn="978-1-61804-245-3" }