Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform

Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform

Paper in proceedings (conference paper)

The aim of this paper is to introduce a new accelerator
developed to address the problem of evolutionary synthesis
of digital circuits at transistor level. The proposed accelerator,
based on recently introduced Xilinx Zynq platform, consists of
a discrete simulator implemented in programmable logic and an
evolutionary algorithm running on a tightly coupled embedded
ARM processor. The discrete simulator was introduced in order to
achieve a good trade-off between the precision and performance
of the simulation of transistor-level circuits. The simulator is
implemented using the concept of virtual reconfigurable circuit
and operates on multiple logic levels which enables to evaluate the
behavior of candidate transistor-level circuits at a reasonable level
of detail. In this work, the concept of virtual reconfigurable circuit
was extended to enable bidirectional data flow which represents
the basic feature of transistor level circuits. According to the
experimental evaluation, the proposed architecture speeds up the
evolution in one order of magnitude compared to an optimized
software implementation. The developed accelerator is utilized
in the evolution of basic logic circuits having up to 5 inputs. It
is shown that solutions competitive to the circuits obtained by
conventional design methods can be discovered.

The aim of this paper is to introduce a new accelerator
developed to address the problem of evolutionary synthesis
of digital circuits at transistor level. The proposed accelerator,
based on recently introduced Xilinx Zynq platform, consists of
a discrete simulator implemented in programmable logic and an
evolutionary algorithm running on a tightly coupled embedded
ARM processor. The discrete simulator was introduced in order to
achieve a good trade-off between the precision and performance
of the simulation of transistor-level circuits. The simulator is
implemented using the concept of virtual reconfigurable circuit
and operates on multiple logic levels which enables to evaluate the
behavior of candidate transistor-level circuits at a reasonable level
of detail. In this work, the concept of virtual reconfigurable circuit
was extended to enable bidirectional data flow which represents
the basic feature of transistor level circuits. According to the
experimental evaluation, the proposed architecture speeds up the
evolution in one order of magnitude compared to an optimized
software implementation. The developed accelerator is utilized
in the evolution of basic logic circuits having up to 5 inputs. It
is shown that solutions competitive to the circuits obtained by
conventional design methods can be discovered.

Xilinx Zynq, transistor-level evolution, evolutionary design, combinational circuit

Xilinx Zynq, transistor-level evolution, evolutionary design, combinational circuit

MRÁZEK, V.; VAŠÍČEK, Z.

2015

12.12.2014

Institute of Electrical and Electronics Engineers

Piscataway

978-1-4799-4480-4

2014 IEEE International Conference on Evolvable Systems Proceedings

9

16

8

http://dx.doi.org/10.1109/ICES.2014.7008716

PID3413423-3