Publication result detail

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

MIČULKA, L.; STRAKA, M.; KOTÁSEK, Z.

Original Title

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

English Title

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.

English abstract

The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.

Keywords

methodology, partial dynamic reconfiguration, relocation, synchronization, limited redundant space

Key words in English

methodology, partial dynamic reconfiguration, relocation, synchronization, limited redundant space

Authors

MIČULKA, L.; STRAKA, M.; KOTÁSEK, Z.

RIV year

2014

Released

29.03.2013

Publisher

IEEE Computer Society

Location

Santander

ISBN

978-0-7695-5074-9

Book

16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

Pages from

227

Pages to

234

Pages count

8

BibTex

@inproceedings{BUT103518,
  author="Lukáš {Mičulka} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area",
  booktitle="16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools",
  year="2013",
  pages="227--234",
  publisher="IEEE Computer Society",
  address="Santander",
  isbn="978-0-7695-5074-9"
}