Publications

• 2020

  KEKELY, L.; CABAL, J.; PUŠ, V.; KOŘENEK, J. Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. In Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: IEEE Computer Society, 2020. p. 49-56. ISBN: 978-1-7281-9535-3.
  Detail | WWW

• 2018

  KUČERA, J.; KEKELY, L.; PUŠ, V.; PIECEK, A.; KOŘENEK, J. Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks. In Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018. p. 177-178. ISBN: 978-1-4503-5902-3.
  Detail | WWW

  CABAL, J.; BENÁČEK, P.; KEKELY, L.; KEKELY, M.; PUŠ, V.; KOŘENEK, J. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: Association for Computing Machinery, 2018. p. 249-258. ISBN: 978-1-4503-5614-5.
  Detail | WWW

• 2016

  MATOUŠEK, D.; KOŘENEK, J.; PUŠ, V. High-speed Regular Expression Matching with Pipelined Automata. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 93-100. ISBN: 978-1-5090-5602-6.
  Detail | WWW

• 2015

  KEKELY, L.; KUČERA, J.; PUŠ, V.; KOŘENEK, J.; VASILAKOS, A. Software Defined Monitoring of Application Protocols. IEEE TRANSACTIONS ON COMPUTERS, 2015, vol. 65, no. 2, p. 615-626. ISSN: 0018-9340.
  Detail | WWW

• 2014

  ZÁVODNÍK, T.; KEKELY, L.; PUŠ, V. CRC based hashing in FPGA using DSP blocks. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 179-182. ISBN: 978-1-4799-4558-0.
  Detail | WWW

  PUŠ, V.; KEKELY, L.; KOŘENEK, J. Design Methodology of Configurable High Performance Packet Parser for FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 189-194. ISBN: 978-1-4799-4558-0.
  Detail | WWW

  KEKELY, L.; PUŠ, V.; BENÁČEK, P.; KOŘENEK, J. Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring. In 2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014). Munich: IEEE Circuits and Systems Society, 2014. p. 264-267. ISBN: 978-3-00-044645-0.
  Detail | WWW

  KEKELY, L.; PUŠ, V.; KOŘENEK, J. Software Defined Monitoring of Application Protocols. In Proceedings of IEEE INFOCOM 2014 - IEEE Conference on Computer Communications. Toronto: IEEE Computer Society, 2014. p. 1725-1733. ISBN: 978-1-4799-3360-0.
  Detail | WWW

• 2012

  KEKELY, L.; PUŠ, V.; KOŘENEK, J. Low-Latency Modular Packet Header Parser for FPGA. ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Austin: Association for Computing Machinery, 2012. p. 77-78. ISBN: 978-1-4503-1685-9.
  Detail | WWW

  PUŠ, V.; KOŘENEK, J. Reducing memory in high-speed packet classification. Proceedings of the 8th International Wireless Communications and Mobile Computing Conference. Limassol: Frederick University, 2012. p. 437-442. ISBN: 978-1-4577-1377-4.
  Detail | WWW

• 2011

  PUŠ, V.; TOBOLA, J.; KAŠTIL, J.; KOŠAŘ, V.; KOŘENEK, J. Netbench - the Framework for Evaluation of Packet Processing Algorithms. Proceedings of the 7th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. New York: IEEE Computer Society, 2011. p. 95-96. ISBN: 978-0-7695-4521-9.
  Detail | WWW

  PUŠ, V.; KAJAN, M.; KOŘENEK, J. Hardware Architecture for Packet Classification with Prefix Coloring. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 231-236. ISBN: 978-1-4244-9753-9.
  Detail | WWW

  PUŠ, V. Packet Classification Algorithms. Počítačové architektury a diagnostika. Stará Lesná: Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava, 2011. p. 157-162. ISBN: 978-80-227-3552-0.
  Detail

• 2010

  KOŘENEK, J.; PUŠ, V. Memory Optimization for Packet Classification Algorithms in FPGA. Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vídeň: IEEE Computer Society, 2010. p. 297-300. ISBN: 978-1-4244-6610-8.
  Detail | WWW

  PUŠ, V. Optimizations of packet classification algorithms. Počítačové architektury & diagnostika 2010. Češkovice: Faculty of Information Technology BUT, 2010. p. 153-158. ISBN: 978-80-214-4140-8.
  Detail

• 2009

  PUŠ, V.; KOŘENEK, J. Fast and scalable packet classification using perfect hash functions. Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays. Association for Computing Machinery. New York: Association for Computing Machinery, 2009. p. 229-236. ISBN: 978-1-60558-410-2.
  Detail | WWW

  PUŠ, V. Algoritmy pro klasifikaci paketů. Počítačové architektury a diagnostika 2009. Zlín: Univerzita Tomáše Bati ve Zlíně, 2009. p. 130-135. ISBN: 978-80-7318-847-4.
  Detail

  KOŘENEK, J.; PUŠ, V. Memory Optimization for Packet Classification Algorithms. Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Association for Computing Machinery. New York: Association for Computing Machinery, 2009. p. 165-166. ISBN: 978-1-60558-630-4.
  Detail | WWW

• 2008

  PUŠ, V. Fast Packet Classification Algorithm in Hardware. Junior Scientist Conference 2008. Vídeň: 2008. p. 65-66. ISBN: 978-3-200-01612-5.
  Detail

  PUŠ, V. Fast Packet Classification Using Perfect Hash Functions. ACM Student Research Competition 2008. Praha: 2008. p. 9-16. ISBN: 978-80-01-04205-2.
  Detail

  PUŠ, V. Rychlá klasifikace paketů s využitím perfektních hashovacích funkcí. Proceedings EEICT 2008. Brno: 2008. p. 236-238. ISBN: 978-80-214-3615-2.
  Detail

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