Course detail
Microprocessors
FEKT-CMICAcad. year: 2010/2011
Logical functions, Bool's algebraic, combination and sequence circuits. Principles of microprocessor. Addressing. Subrutins, interrups, stack utilisation. Von Neuman and harward conception of computer. Overlapping and pipelining. Superscalar architecture. CISC a RISC processors.
Microcontrollers Motorola HCS12: SW model. Instruction set. Peripherals: Parallel Input/Output, A/D convertor, timer system, SCI, SPI. Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display. Segmentation, paging, memory virtualisations. Intel Pentium: Addressing modes. Virtual addressing. Real mode and protected mode. Memory protection. Gates. Proces switching. Paging unit. Interrupts. Embedded systems.
Language of instruction
Number of ECTS credits
Mode of study
Guarantor
Learning outcomes of the course unit
Prerequisites
Co-requisites
Planned learning activities and teaching methods
Assesment methods and criteria linked to learning outcomes
Final examination is evaluated by 60 points at maximum.
Course curriculum
2. Combination logical circuits (switches, decoders, multiplectors, demultiplectors). Sequencal logical circuits: flip-flop.
3. Sequencal logical circuits: Huffman's model of automat, Mealy automat, Moor automat. Registers, counters, deviders, shift registers.
4. Memories. Computer block diagram, CPU - ALU, controller, registers. Microprocessor, microcomputer, microcontroller, DSP. Base principle microprocessor working. Clock cycle, phase, machine cycle, instruction cycle.
4. Addressing. Subrutins, interrupts, stacks utilisation. Von Neumann, Harvard modified Harvard microprocessor architectures. Overlapping. Pipelining.
5. Microcontrollers Motorola HCS12 family: Programmer model, ALU. Addressing modes. Operational modes and memory maps.
6. HCS12: Operating modes. Ports, MEBI units, Key Wake up function, PIM units. CRG units (oscilators, PLL, real-time interrup (RTI), Watchdog (COP)).
7. HCS12: A/D convertor. Timer subsystem: Imput capture function. Output compare function. Pulse accumulatos.
8.HCS12: Serial Comunication Interface (SCI). Serial Peripheral Interface (SPI). Low power modes WAIT and STOP.
9. HCS12: Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display.
10. Segmentation, paging and virtual memory. Intel IA32 (I386) architecture: Programmer model. Addressing modes. Memory addressing and I/O addressing.
11. IA32: Privilegy levels. Local and global address space. GDI and LDI tables. Logical address, linear address. Segment descriptors. Data segment Acces.
12. IA32: Calling instruction segment. Gates. Task switching. Interrupts in real and protected mode. Paging unit.
13. Architecture of Intel pentium P6. MMX, SSE, SSE2, SSE3 instructions. New states of art in Intel microprocessors. Embedded systems.
Work placements
Aims
Specification of controlled education, way of implementation and compensation for absences
Recommended optional programme components
Prerequisites and corequisites
Basic literature
Recommended reading
Classification of course in study plans
Type of course unit
Lecture
Teacher / Lecturer
Syllabus
2. Combination logical circuits (switches, decoders, multiplectors, demultiplectors). Sequencal logical circuits: flip-flop.
3. Sequencal logical circuits: Huffman's model of automat, Mealy automat, Moor automat. Registers, counters, deviders, shift registers.
4. Memories. Computer block diagram, CPU - ALU, controller, registers. Microprocessor, microcomputer, microcontroller, DSP. Base principle microprocessor working. Clock cycle, phase, machine cycle, instruction cycle.
4. Addressing. Subrutins, interrupts, stacks utilisation. Von Neumann, Harvard modified Harvard microprocessor architectures. Overlapping. Pipelining.
5. Microcontrollers Motorola HCS12 family: Programmer model, ALU. Addressing modes. Operational modes and memory maps.
6. HCS12: Operating modes. Ports, MEBI units, Key Wake up function, PIM units. CRG units (oscilators, PLL, real-time interrup (RTI), Watchdog (COP)).
7. HCS12: A/D convertor. Timer subsystem: Imput capture function. Output compare function. Pulse accumulatos.
8.HCS12: Serial Comunication Interface (SCI). Serial Peripheral Interface (SPI). Low power modes WAIT and STOP.
9. HCS12: Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display.
10. Segmentation, paging and virtual memory. Intel IA32 (I386) architecture: Programmer model. Addressing modes. Memory addressing and I/O addressing.
11. IA32: Privilegy levels. Local and global address space. GDI and LDI tables. Logical address, linear address. Segment descriptors. Data segment Acces.
12. IA32: Calling instruction segment. Gates. Task switching. Interrupts in real and protected mode. Paging unit.
13. Architecture of Intel pentium P6. MMX, SSE, SSE2, SSE3 instructions. New states of art in Intel microprocessors. Embedded systems.
Exercise in computer lab
Teacher / Lecturer
Syllabus
2. Floating point numbers by IEEE-754 standard. Logical function simplification, binary sumation circuit design.
3. Sequece logical circuit design.
4. Assembly language prougram - addition and substraction 16 bit and 32 bit numbers.
5. Assembly language program - moving field of numbers. Assembly language program for sorting field of numbers.
6. Assembly language program - multiplication two 16 bit numbers with using shift instructions.
Assembler programme for multiplication two 16 bit numbers with using MUL instructions.
7. Assembly language program - stack utilisation.
8. C language program - utilisation of binary HCS12 I/O ports.
9. C programme - utilisation of HCS12 Real Time Interrupt.
10. C programme - utilisation of HCS12 serial comunication interface.
11. C programme - utilisation of HCS12 A/D convertor.
12.C programme - utilisation of HCS12 Output Compare and Imput Capture functions.
13. Final test.