Course detail

Advanced RISC-V Architecture Design

FEKT-MPA-RSC2Acad. year: 2025/2026

The course material will convey both technical and industry requirements to enable proper engineering architectural decisions as well as implementation.
Topics include:
1. General-Purpose Advanced Computer Architectures
- Super Scaler
- Out of Order
- Prediction
- Speculation (Tomasulo’s Algorithm)
2. Understanding product goals
- Google’s Tensorflow Engine
- Microsoft’s Catapult malleable accelerators
- Google’s Pixel Engine
3. Caches and Data Coherency
4. Very Large Instruction Word (VLIW)
5. Vector Engines
6. Near Memory Accelerators
7. Systolic Arrays 

Language of instruction

English

Number of ECTS credits

Mode of study

Not applicable.

Guarantor

doc. Ing. Lukáš Fujcik, Ph.D.

Department

Department of Microelectronics (UMEL)

Entry knowledge

- Logic Design
- Undergraduate Computer Architecture or Computer Organization course
- Programming in C (or C++)
- Basics of RISCV Architecture course  

Rules for evaluation and completion of the course

There will be a mid-term and final examination.  
The mid-term and final examination are to be done using individual effort alone.

The course grade will be based on in-class participation, homework assignments, quizzes, course project, and 2 exams. The grade proportions are as follows:
• Homework 15%
• Project 40%
• Mid-Term 20%
• Final Exam: 25% 

Upon the professor’s discretion, assignment of grades can be based on both absolute and relative standards if it would be helpful to the overall class.  To receive an A grade in this assignment of grades option, a student must show mastery of the material and need to acquire more than 90% of the points possible.  A student earning less than 50% of the points possible will be given a failing grade.  In between these marks, grades will be assigned on a curve using a mean and standard deviation method.

 

Aims

1. Describe general-purpose advanced architectures and why they are still used
2. Select the best advanced architecture to accelerate a particular algorithm that meets the end product objectives
3. Design the advanced architecture effectively into a system
4. Understand Roofline modeling and how to use them to effectively improve system level performance
5. Implement a near-memory accelerator and a systolic array processor  

Study aids

electronic texts, presentations, video tutorials 

 

Prerequisites and corequisites

Not applicable.

Basic literature

Computer Organization and Design RISC-V Edition: The Hardware Software Interface, David A. Patterson (Author), John L. Hennessy (Author), 2023, 736 pages, ISBN 978-0128203316 (EN)
Digital Design and Computer Architecture, RISC-V Edition: RISC-V Edition, Sarah Harris, 2021, 592 pages, ISBN 978-0128200643 (EN)
Volnei A. Pedroni, Circuit Design with VHDL, third edition, 2023, 608 pages, ISBN 978-0262042642 (EN)

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme MPC-NCP Master's 2 year of study, summer semester, compulsory-optional

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

doc. Ing. Lukáš Fujcik, Ph.D.

Syllabus

1. General Purpose Advanced Computer Architectures – What are they and how did we get here
2. Super-Scaler versus VLIW
3. Performance via Prediction
4. Out-of-Order and Speculation
5. Tomasulo’s Aglorithm
6. Case study: Google’s TensorFlow processor. Near-Memory accelerators.
7. Near-Memory accelerators
8. Case Study: Google’s Pixel Engine . Systolic Array Processors.
9. Systolic Array Processors
10. Case Study:  Microsoft’s Catapult malleable accelerators
11. System level design considerations. Roofline modeling. Cache Coherency
12. System level design considerations. Advanced cache architectures.
13. Course Project demos   

Exercise in computer lab

26 hod., compulsory

Teacher / Lecturer

doc. Ing. Lukáš Fujcik, Ph.D.

Syllabus

Through doing or explaining things to others, you can achieve a much deeper understanding.  Over an eight-week project, you will have an opportunity to obtain a deeper understanding of an advanced computer architecture using a RISC-V core through the development of either a near-memory accelerator, systolic array processor, or through the addition of a Very Large Instruction Word (VLIW) processor that significantly improves the performance of an Artificial Intelligence (AI), Crytpo, or Digital Signal Processing (DSP) application.  It will be a team project of two students per team.  The grading of this project will include a demonstration of your RISC-V core which will include interview grading.