Course detail

Digital Circuits

FEKT-BKC-DIOAcad. year: 2023/2024

Fundamentals of digital circuits. VHDL language and general syntax. Concurrent statements, design methodology and examples. Logic hazards, their elimination and avoiding. Sequential statements, design methodology and examples. Metastability. State machine theory and design methodology. Translation of VHDL code to schematic representation (methodology understanding). Practical design of sequential systems and state machines.

Language of instruction


Number of ECTS credits


Mode of study

Not applicable.

Entry knowledge

Student should be able to:
- Describe the basic logic gates NAND, NOR, AND, OR, INV – logic functions, truth tables etc.
- Conversion from various number representations
- Describe CMOS technology process and how the NMOS and PMOS transistor work.
- Fundamentals of flowcharts and their utilization

Rules for evaluation and completion of the course

30 points for work during semester.
70 points for final exam.

The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.


Aim of this course is make students familiar with recent digital world by balanced using of theory, intuitive approach and practical exercises performed on development kits with FPGA circuit. Students learn the methodology of digital circuit design which can be applied on any platforms such as FGPA, ASIC or discrete solution.
Student will be able to:
- explain fundamentals of combinational and sequential circuits and how these circuits manually design
- describe digital circuits by using VHDL
- design state machines and their design and methodology
- draw the schematic representation from VHDL code
- explain synchronous circuit design methodology

Study aids

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Pinker, J., Poupa, M., Číslicové systémy a jazyk VHDL, BEN - Technická literatura, 2006, ISBN: 80-7300-198-5 (CS)
Skahill, K., VHDL for Programmable Logic, Addison-Wesley, 1996, ISBN 0-201-89573-0. (EN)

Recommended reading

Not applicable.


Classification of course in study plans

  • Programme BKC-MET Bachelor's, 2. year of study, summer semester, compulsory

Type of course unit



26 hours, optionally

Teacher / Lecturer

Laboratory exercise

39 hours, compulsory

Teacher / Lecturer