Course detail

Design of Computer Systems

FIT-INPAcad. year: 2018/2019

Principles of a processor. Von Neumann computer. Data types, formats and coding. Instructions, formats, coding and addressing, instruction set architecture. VHDL models of algorithms and subsystems. Pipelining. Arithmetic and logic operations. Sequencer: basic function, hard-wired and microprogram implementation. Memories: types, organization, control. Memory hierarchy, cache memory. Peripheral units, buses and bus control. Performance evaluation. Reliability of computer systems. Introduction to parallel architectures.

Language of instruction

Czech, English

Number of ECTS credits

Mode of study

Not applicable.

Guarantor

prof. Ing. Lukáš Sekanina, Ph.D.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

Students are able to describe functionality of the operation, memory and control units and their communication in a computer. They are familiar with VHDL.
Understanding of development trends and possibilities of computer technology.

Prerequisites

Not applicable.

Co-requisites

Boolean algebra, basics of electrical circuits, basic computer elements, design of combinatorial and sequential circuits.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Written final exam, mid-term exam and submitting projects in due dates.
Exam prerequisites:
For receiving the credit and thus for entering the exam, students have to get at least 20 points during the semester.

Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.

Course curriculum

Not applicable.

Work placements

Not applicable.

Aims

To give the students knowledge of organization and functioning of a (single core) processor, in particular, the principles of the operation, memory and control units, the algorithms with fixed and floating point number systems, the subsystem communication level, and integration of the processor to a parallel system.

Specification of controlled education, way of implementation and compensation for absences

Within this course, attendance on the lectures and demonstrations is not monitored. The knowledge of students is examined by the projects, the mid-term exam and by the final exam. The minimal number of points which can be obtained from the final exam is 20. Otherwise, no points will be assigned to a student. In the case of a reported barrier preventing the student to perform scheduled activity, the guarantor can allow the student to perform this activity on an alternative date.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Basic literature

Drábek V.: Výstavba počítačů, skripta VUT v Brně, PC-DIR, Brno, 1995. (CS)
Hamacher, C., Vranesic, Z., Zaky, S., N. Manjikian: Computer Organization and Embedded Systems, 6th edition, McGraw Hill, 2012, ISBN-13: 978-0-07-338065-0
Hennessy J. L., Patterson D. A.: Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann Publ., 1996, and new editions, e.g. the 5th ed. from 2012.

Recommended reading

Pinker J., Poupa M.: Číslicové systémy a jazyk VHDL, BEN - technická literatura, Praha, 2006. (CS)

Classification of course in study plans

  • Programme IT-BC-3 Bachelor's

    branch BIT , 2 year of study, winter semester, compulsory

Type of course unit

 

Lecture

39 hod., optionally

Teacher / Lecturer

prof. Ing. Lukáš Sekanina, Ph.D.
doc. Ing. Zdeněk Vašíček, Ph.D.
doc. Ing. Michal Bidlo, Ph.D.

Syllabus

  • Introduction, processor and its function.
  • Data representation.
  • Instruction sets, register structures.
  • Modelling in VHDL.
  • Pipeline processing.
  • Algorithms of fixed point operations.
  • Algorithms of floating point operations, iterative algorithms.
  • Controllers.
  • Memories, cache memory.
  • Buses, peripheral interfacing and control.
  • Computer performance and performance evaluation.
  • Reliability of computer systems.
  • Introduction to parallel architectures.

Fundamentals seminar

12 hod., compulsory

Teacher / Lecturer

doc. Ing. Michal Bidlo, Ph.D.
doc. Ing. Zdeněk Vašíček, Ph.D.

Syllabus

  • VHDL - introduction
  • VHDL - synthesizable code
  • Introduction to FITkit
  • Processor in VHDL
  • Huffman code, Hamming code
  • Modular arithmetic, adders
  • Multipliers
  • Division
  • Iterative algorithms
  • Performance evaluation, reliability
  • Parallel architectures

Project

14 hod., compulsory

Teacher / Lecturer

doc. Ing. Michal Bidlo, Ph.D.
doc. Ing. Zdeněk Vašíček, Ph.D.

Syllabus

  • Two projects will be assigned during the semester.