Course detail
Embedded Systems and Microprocessors
FEKT-BPC-MICAcad. year: 2018/2019
The course is focused on fundamentals of microprocessor and embedded systems. Students are familiarized with basic principals of microprocessor function, on-chip peripheral subsystems of microcontrollers, memory systems and memory management. The students will achieve practical experience with programing of the embedded systems in assembler and C language.
Language of instruction
Czech
Number of ECTS credits
6
Mode of study
Not applicable.
Guarantor
Learning outcomes of the course unit
Graduate should be able to:
- explain difference between microprocessor, microcontroller, DSP and signal controller,
- enumerat and describe methods of I/O peripherals.
- create software for simple embedded system in assembly and C language,
- expaline principles and describe characteristics of SRAM, DRAM, SDRAM, DDR RAM, ROM, EPROM, EEPROM, FLASH (NOR, NAND FLASH), FeRAM, MRAM memories,
- describe memory hierarchy and explain usage of cache memory,
- explain segmentation, paging, swapping and virtual memory,
- design connection of external memory with microcontroller,
- explain difference between microprocessor, microcontroller, DSP and signal controller,
- enumerat and describe methods of I/O peripherals.
- create software for simple embedded system in assembly and C language,
- expaline principles and describe characteristics of SRAM, DRAM, SDRAM, DDR RAM, ROM, EPROM, EEPROM, FLASH (NOR, NAND FLASH), FeRAM, MRAM memories,
- describe memory hierarchy and explain usage of cache memory,
- explain segmentation, paging, swapping and virtual memory,
- design connection of external memory with microcontroller,
Prerequisites
The student should be able to create simple C language program and explaine function of the elementary electronic parts.
Co-requisites
Not applicable.
Planned learning activities and teaching methods
Techning methods include lectures and laboratory lectures. Students have to create assignments during the laboratory lectures.
Assesment methods and criteria linked to learning outcomes
Up to 40 points for the laboratory lectures (2 tests up to 30 points, assignments up to 10 points).
Up to 60 points for the final oral examination. Minimal needed points from oral examination is 20.
Up to 60 points for the final oral examination. Minimal needed points from oral examination is 20.
Course curriculum
1. Introduction to the course. Von Neumann architecture, base parts of the computer. Base computer cycle. Harvard architecture, modified Harvard architecture. Microprocessor, microcontroller, digital signal processor, digital signal controller.
2. Instruction set, type of instructions. Addressing modes. Machine code.
3. Assembly language: mnemonic codes, assembly directives, labels. Instruction set of microcontrollers used in laboratory lectures.
4. Subroutines, arguments passing, saving return values, stack. Subroutine vs. macro.
5. Principles of I/O handling: busy waiting, interrupt, DMA. Memory map, separated and hybrid peripherals. Interrupt servicing. Mask, non-mask and pseudo-mask interrupts. Nested interrupts. Processor RESET.
6. Using of C language for embedded programming and programming of I/O operations. Peripheral subsystems of microcontrollers: ports, system clock generating units, real-time clocks, watchdogs.
7. Peripheral subsystems of microcontrollers: counters and timers, Input Capture and Output Compare functions, time interval measurement. PWM subsystems.
8. Peripheral subsystems of microcontrollers: A/D, D/A convertors, SCI (UART), SPI, IIC.
9. Principle a characteristics SRAM, DRAM, SDRAM, DDR RAM memories.
10. Principle a characteristics ROM, EPROM, EEPROM, FLASH (NOR, NAND FLASH), FeRAM, MRAM memories.
11. Embedded system memory subsystem: Serial vs. parallel memory interface. Address decoder. Incomplete address decoding – memory mirroring. Memory hierarchy. Cache memories.
12. Pipelining. Superscalar architecture. Multiprocessor systems. CISC, RISC and Post RISC processors.
13. Memory management: Address space. Logical and physical address, MMU. Contiguous memory allocation, segmentation, paging. TLB. Swapping. Virtual memory.
2. Instruction set, type of instructions. Addressing modes. Machine code.
3. Assembly language: mnemonic codes, assembly directives, labels. Instruction set of microcontrollers used in laboratory lectures.
4. Subroutines, arguments passing, saving return values, stack. Subroutine vs. macro.
5. Principles of I/O handling: busy waiting, interrupt, DMA. Memory map, separated and hybrid peripherals. Interrupt servicing. Mask, non-mask and pseudo-mask interrupts. Nested interrupts. Processor RESET.
6. Using of C language for embedded programming and programming of I/O operations. Peripheral subsystems of microcontrollers: ports, system clock generating units, real-time clocks, watchdogs.
7. Peripheral subsystems of microcontrollers: counters and timers, Input Capture and Output Compare functions, time interval measurement. PWM subsystems.
8. Peripheral subsystems of microcontrollers: A/D, D/A convertors, SCI (UART), SPI, IIC.
9. Principle a characteristics SRAM, DRAM, SDRAM, DDR RAM memories.
10. Principle a characteristics ROM, EPROM, EEPROM, FLASH (NOR, NAND FLASH), FeRAM, MRAM memories.
11. Embedded system memory subsystem: Serial vs. parallel memory interface. Address decoder. Incomplete address decoding – memory mirroring. Memory hierarchy. Cache memories.
12. Pipelining. Superscalar architecture. Multiprocessor systems. CISC, RISC and Post RISC processors.
13. Memory management: Address space. Logical and physical address, MMU. Contiguous memory allocation, segmentation, paging. TLB. Swapping. Virtual memory.
Work placements
Not applicable.
Aims
The aim of the course is to give base information about principles of the microprocessors systems, subsystems of microcontrollers and design of embedded system software.
Specification of controlled education, way of implementation and compensation for absences
The laboratory lectures are mandatory, the properly excused missed laboratory lectures can be compensate.
Recommended optional programme components
Not applicable.
Prerequisites and corequisites
- compulsory prerequisite
Introduction to Programming
Basic literature
Not applicable.
Recommended reading
LIČEV, L., MORKES D.: Procesory - architektura, funkce, použití. Brno: Computer press, 1999. 260 s. ISBN 80-7226-172-X. (CS)
PINKER, J., POUPA, M.: Číslicové systémy a jazyk VHDL. Praha: BEN, 2006. 349 s. ISBN 80-7300-198-5. (CS)
PINKER, J., POUPA, M.: Číslicové systémy a jazyk VHDL. Praha: BEN, 2006. 349 s. ISBN 80-7300-198-5. (CS)
Classification of course in study plans
- Programme BPC-AMT Bachelor's 2 year of study, summer semester, compulsory
Type of course unit
Lecture
26 hod., optionally
Teacher / Lecturer
Syllabus
1. Mathematical logic, logical function, Boole's algebraic. Table, map and algebraical form of logical function. Simplification of logical functions.
2. Combination logical circuits (switches, decoders, multiplectors, demultiplectors). Sequencal logical circuits: flip-flop.
3. Sequencal logical circuits: Huffman's model of automat, Mealy automat, Moor automat. Registers, counters, deviders, shift registers.
4. Memories. Computer block diagram, CPU - ALU, controller, registers. Microprocessor, microcomputer, microcontroller, DSP. Base principle microprocessor working. Clock cycle, phase, machine cycle, instruction cycle.
4. Addressing. Subrutins, interrupts, stacks utilisation. Von Neumann, Harvard modified Harvard microprocessor architectures. Overlapping. Pipelining.
5. Microcontrollers Motorola HCS12 family: Programmer model, ALU. Addressing modes. Operational modes and memory maps.
6. HCS12: Operating modes. Ports, MEBI units, Key Wake up function, PIM units. CRG units (oscilators, PLL, real-time interrup (RTI), Watchdog (COP)).
7. HCS12: A/D convertor. Timer subsystem: Imput capture function. Output compare function. Pulse accumulatos.
8.HCS12: Serial Comunication Interface (SCI). Serial Peripheral Interface (SPI). Low power modes WAIT and STOP.
9. HCS12: Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display.
10. Segmentation, paging and virtual memory. Intel IA32 (I386) architecture: Programmer model. Addressing modes. Memory addressing and I/O addressing.
11. IA32: Privilegy levels. Local and global address space. GDI and LDI tables. Logical address, linear address. Segment descriptors. Data segment Acces.
12. IA32: Calling instruction segment. Gates. Task switching. Interrupts in real and protected mode. Paging unit.
13. Architecture of Intel pentium P6. MMX, SSE, SSE2, SSE3 instructions. New states of art in Intel microprocessors. Embedded systems.
2. Combination logical circuits (switches, decoders, multiplectors, demultiplectors). Sequencal logical circuits: flip-flop.
3. Sequencal logical circuits: Huffman's model of automat, Mealy automat, Moor automat. Registers, counters, deviders, shift registers.
4. Memories. Computer block diagram, CPU - ALU, controller, registers. Microprocessor, microcomputer, microcontroller, DSP. Base principle microprocessor working. Clock cycle, phase, machine cycle, instruction cycle.
4. Addressing. Subrutins, interrupts, stacks utilisation. Von Neumann, Harvard modified Harvard microprocessor architectures. Overlapping. Pipelining.
5. Microcontrollers Motorola HCS12 family: Programmer model, ALU. Addressing modes. Operational modes and memory maps.
6. HCS12: Operating modes. Ports, MEBI units, Key Wake up function, PIM units. CRG units (oscilators, PLL, real-time interrup (RTI), Watchdog (COP)).
7. HCS12: A/D convertor. Timer subsystem: Imput capture function. Output compare function. Pulse accumulatos.
8.HCS12: Serial Comunication Interface (SCI). Serial Peripheral Interface (SPI). Low power modes WAIT and STOP.
9. HCS12: Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display.
10. Segmentation, paging and virtual memory. Intel IA32 (I386) architecture: Programmer model. Addressing modes. Memory addressing and I/O addressing.
11. IA32: Privilegy levels. Local and global address space. GDI and LDI tables. Logical address, linear address. Segment descriptors. Data segment Acces.
12. IA32: Calling instruction segment. Gates. Task switching. Interrupts in real and protected mode. Paging unit.
13. Architecture of Intel pentium P6. MMX, SSE, SSE2, SSE3 instructions. New states of art in Intel microprocessors. Embedded systems.
Exercise in computer lab
39 hod., compulsory
Teacher / Lecturer
Syllabus
1. Decimal, hexadecimal and binary numbers. Addition, substraction binary numbers. First complemment. Miltiplication and division binary numbers.
2. Floating point numbers by IEEE-754 standard. Logical function simplification, binary sumation circuit design.
3. Sequece logical circuit design.
4. Assembly language prougram - addition and substraction 16 bit and 32 bit numbers.
5. Assembly language program - moving field of numbers. Assembly language program for sorting field of numbers.
6. Assembly language program - multiplication two 16 bit numbers with using shift instructions.
Assembler programme for multiplication two 16 bit numbers with using MUL instructions.
7. Assembly language program - stack utilisation.
8. C language program - utilisation of binary HCS12 I/O ports.
9. C programme - utilisation of HCS12 Real Time Interrupt.
10. C programme - utilisation of HCS12 serial comunication interface.
11. C programme - utilisation of HCS12 A/D convertor.
12.C programme - utilisation of HCS12 Output Compare and Imput Capture functions.
13. Final test.
2. Floating point numbers by IEEE-754 standard. Logical function simplification, binary sumation circuit design.
3. Sequece logical circuit design.
4. Assembly language prougram - addition and substraction 16 bit and 32 bit numbers.
5. Assembly language program - moving field of numbers. Assembly language program for sorting field of numbers.
6. Assembly language program - multiplication two 16 bit numbers with using shift instructions.
Assembler programme for multiplication two 16 bit numbers with using MUL instructions.
7. Assembly language program - stack utilisation.
8. C language program - utilisation of binary HCS12 I/O ports.
9. C programme - utilisation of HCS12 Real Time Interrupt.
10. C programme - utilisation of HCS12 serial comunication interface.
11. C programme - utilisation of HCS12 A/D convertor.
12.C programme - utilisation of HCS12 Output Compare and Imput Capture functions.
13. Final test.