Course detail

Functional Verification of Digital Systems

FIT-FVSAcad. year: 2017/2018

Importance of functional verification. Requirements specification and verification plan. Simulation and creating testbenches. Functional verification and its methods (pseudo-random stimuli generation, coverage-driven verification, asserion-based verification, self-checking mechanisms). Verification methodologies and SystemVerilog language. Reporting and correction of errors. Emulation and FPGA prototyping.

Language of instruction

Czech

Number of ECTS credits

Mode of study

Not applicable.

Guarantor

doc. Ing. Zdeněk Kotásek, CSc.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to OVM/UVM verification methodology.

Prerequisites

Digital system design, basic programming skills.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Requirements for class accreditation are not defined.

Course curriculum

    Syllabus of lectures:
    1. History of functional verification, HDL and HVL languages. Requirements specification and the verification plan.
    2. Testing digital systems using simulation. VHDL language. Creating testbenches. HDL simulators.
    3. Introduction to functional verification. Functional verification techniques.
    4. Verification methodologies. HVL languages.
    5. Pseudo-random stimuli generation, direct tests, constraints.
    6. Coverage-driven verification. Coverage metrics. Coverage measurement and analysis.
    7. Self-checking mechanisms.
    8. Assertions. Assertion languages. Errors reporting.
    9. Assertion-based verification.
    10. Emulation and prototyping.
    11. Hardware debugging.
    12. Industry lecture.
    13. Special cases in verification of digital systems. Other verification approaches. Challenges and open problems in verification.

    Syllabus of laboratory exercises:
    1. Creating testbench for arithmetic-logic unit (ALU).
    2. Creating verification environment for ALU.
    3. Coverage-driven verification of ALU.
    4. Assertion-based verification of ALU.

    Syllabus - others, projects and individual work of students:
    Design and implementation of verification environment for a selected digital systém.

Work placements

Not applicable.

Aims

Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (OVM, UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.

Specification of controlled education, way of implementation and compensation for absences

Labs and project in due dates.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

* Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175. * Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217 * Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141. * Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418. 

Recommended reading

Přednáškové materiály v elektronické formě.

Classification of course in study plans

  • Programme IT-MSC-2 Master's

    branch MMI , 0 year of study, summer semester, elective
    branch MBI , 0 year of study, summer semester, elective
    branch MSK , 0 year of study, summer semester, elective
    branch MMM , 0 year of study, summer semester, elective
    branch MBS , 0 year of study, summer semester, elective
    branch MPV , 0 year of study, summer semester, elective
    branch MIS , 0 year of study, summer semester, elective
    branch MIN , 0 year of study, summer semester, elective
    branch MGM , 0 year of study, summer semester, elective

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

doc. Ing. Zdeněk Kotásek, CSc.

Syllabus

  1. History of functional verification, HDL and HVL languages. Requirements specification and the verification plan.
  2. Testing digital systems using simulation. VHDL language. Creating testbenches. HDL simulators.
  3. Introduction to functional verification. Functional verification techniques.
  4. Verification methodologies. HVL languages.
  5. Pseudo-random stimuli generation, direct tests, constraints.
  6. Coverage-driven verification. Coverage metrics. Coverage measurement and analysis.
  7. Self-checking mechanisms.
  8. Assertions. Assertion languages. Errors reporting.
  9. Assertion-based verification.
  10. Emulation and prototyping.
  11. Hardware debugging.
  12. Industry lecture.
  13. Special cases in verification of digital systems. Other verification approaches. Challenges and open problems in verification.

Laboratory exercise

8 hod., compulsory

Teacher / Lecturer

doc. Ing. Zdeněk Kotásek, CSc.

Syllabus

  1. Creating testbench for arithmetic-logic unit (ALU).
  2. Creating verification environment for ALU.
  3. Coverage-driven verification of ALU.
  4. Assertion-based verification of ALU.

Project

18 hod., optionally

Teacher / Lecturer

doc. Ing. Zdeněk Kotásek, CSc.