Course detail
Programmable Logic Devices
FEKT-MPLDAcad. year: 2012/2013
The course is aimed to extend the knowledge of digital technique. Types of programmable devices: SPLD, CPLD and FPGA devices. Special function blocks used in PLD devices. Text description (HDL languages) and graphical description of PLD subsystems. CAD development systems and their use for simulation of digital subsystems (combinational circuits, counters, state machines), synthesis and implementation into CPLD and FPGA devices. Functional verification of designed subsystems by programming laboratory kits.
Language of instruction
Number of ECTS credits
Mode of study
Guarantor
Department
Learning outcomes of the course unit
Prerequisites
Co-requisites
Planned learning activities and teaching methods
Assesment methods and criteria linked to learning outcomes
Course curriculum
Architecture of FPGAs, FPGA on the market, future of FPGAs.
Using microcontrollers and other advanced features of FPGAs (gigabit transceivers, MAC, PCI-Express), system on chip (SoC).
VHDL basics, typical coding examples, IP cores and its usage.
Verification: testbench, behavioral simulation, post PAR simulation.
Design of PLD-based systems: power, signal integrity, packing, PCB.
Work placements
Aims
Specification of controlled education, way of implementation and compensation for absences
Recommended optional programme components
Prerequisites and corequisites
Basic literature
KOLOUCH, J.: Programovatelné logické obvody a návrh jejich aplikací v jazyku VHDL - počítačové cvičení. [Skriptum FEKT VUT v Brně.] MJ servis, Brno 2005 (CS)
Recommended reading
Classification of course in study plans
- Programme EEKR-M Master's
branch M-MEL , 2 year of study, summer semester, elective interdisciplinary
branch M-SVE , 2 year of study, summer semester, elective interdisciplinary
branch M-TIT , 1 year of study, summer semester, elective interdisciplinary
branch M-EST , 1 year of study, summer semester, elective specialised - Programme EEKR-M Master's
branch M-TIT , 1 year of study, summer semester, elective interdisciplinary
branch M-EST , 1 year of study, summer semester, elective specialised
branch M-MEL , 1 year of study, summer semester, elective interdisciplinary
branch M-SVE , 1 year of study, summer semester, elective interdisciplinary - Programme EEKR-CZV lifelong learning
branch EE-FLE , 1 year of study, summer semester, elective specialised
Type of course unit
Lecture
Teacher / Lecturer
Syllabus
Simple PLDs, their functional blocks, macrocells of GAL 16V8 and 20V8 devices. Other SPLD types, their labelling and parameters
Complex PLD and FPGA devices - structure, basic properties
Introduction to VHDL programming language, synthesis and implementation (translation, mapping, place and route), constraints
Asynchronous (combinational) and synchronous (sequence) logic systems in PLDs.
Counters: binary, decimal (one- and bidirectional, with shortened cycle), Gray counter, LFSR – properties, HDL description
State machines (SM): Moore and Mealy type, HDL description, their compilation to SOP form
Simplifying of SM - equivalent states, their finding. State coding for PLDs and FPGAs. Algorithmic description of SM
Timing in programmable devices, pipelining, register retiming. Metastability, usage of reset signal and corresponding HDL description
FPGA devices - additional blocks: I/O standards, memory elements, blocks for frequency synthesis and for further handling of clock signals, fast serial communication, DSP blocks
Implementation of processors, use of intellectual property blocks
Boundary scan, PLD configuration, PCB design for PLD.
Exercise in computer lab
Teacher / Lecturer
Syllabus
Basic functions, combinational logic (decoding)
Hierarchical design, usage of schematic
Implementation of sequential systems (counters)
State machines and their VHDL description
Structural description, testbench, simulation
LFSR counter, timing parameters, power consumption of FPGA
Usage of IP cores
Usage of ChipScope tool
Microprocessors in FPGA - PicoBlaze, MicroBlaze