Publication detail

Using Petri Nets for RT Level Digital Systems Test Scheduling

ŠKARVADA, J. RŮŽIČKA, R.

Original Title

Using Petri Nets for RT Level Digital Systems Test Scheduling

Type

conference paper

Language

English

Original Abstract

The paper deals with test scheduling for digital systems. Approach with C/E Petri nets is presented and formal model of digital system under test is introduced. Main purpose of this model is identification of structural conflicts and dead locks that may occur during test application phase. The digital system is analyzed on register transfer (RT) level. The obtained results can be used for digital system design partitioning. In this step individual blocks of logic are identified. Finally concurrent test for non-conflicting blocks of logic is scheduled. The advantage of this approach is, that with partitioned circuit, it is possible to view digital circuit design as system on chip (SOC) design and use existing test scheduling methods for SOC.

Keywords

Digital circuit, C/E Petri Net, test scheduling, I-paths, structural conflicts

Authors

ŠKARVADA, J.; RŮŽIČKA, R.

RIV year

2006

Released

25. 4. 2006

Location

Ostrava

ISBN

80-86840-20-4

Book

Proceedings of 1st International Workshop on Formal Models (WFM'06)

Pages from

79

Pages to

86

Pages count

8

BibTex

@inproceedings{BUT22189,
  author="Jaroslav {Škarvada} and Richard {Růžička}",
  title="Using Petri Nets for RT Level Digital Systems Test Scheduling",
  booktitle="Proceedings of 1st International Workshop on Formal Models (WFM'06)",
  year="2006",
  pages="79--86",
  address="Ostrava",
  isbn="80-86840-20-4"
}