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Project detail
Duration: 01.01.2022 — 31.12.2025
Funding resources
Ministerstvo vnitra ČR - Strategická podpora rozvoje bezpečnostního výzkumu ČR 2019–2025 (IMPAKT 1) PODPROGRAMU 1 SPOLEČNÉ VÝZKUMNÉ PROJEKTY (BV IMP1/2VS)
- whole funder (2021-12-01 - not assigned)
On the project
Description in EnglishThe project addresses current shortage of tools for the analysis and verification of security certifications for devices used in cybersecurity. In particular, for hardware devices implementing cryptographic algorithms, such as smartcards, it is currently difficult in the Czech Republic to verify the declared levels of security reliably. That prevents performing risk analysis of systems based on these devices and, therefore, their use by national security agencies and critical information infrastructures. The project will deliver novel hardware and software tools based on the AI principles that will be usable for specific steps in automated verification of device security with respect to either declared certification or manufacturer’s/vendor’s statement.
Key words in EnglishCybersecurity, cryptography, certification, artificial intelligence, analysis, security evaluation
Mark
VJ02010010
Default language
Czech
People responsible
Martinásek Zdeněk, doc. Ing., Ph.D. - fellow researcherHajný Jan, doc. Ing., Ph.D. - principal person responsible
Units
Department of Telecommunications- (2021-04-15 - not assigned)
Results
JEDLIČKA, P.; HAJNÝ, J. VHDL-based implementation of CRYSTALS-Kyber components on FPGA. In Proceedings II of the 28th Conference STUDENT EEICT 2022 Selected Papers. 1st. Brno: Brno University of Technology, Faculty of Electrical Engineering and Communication, 2022. p. 297-301. ISBN: 978-80-214-6030-0.Detail
MARTINÁSEK, Z.; MALINA, L.; HAJNÝ, J.; JEDLIČKA, P.; GERLICH, T. Postup a výzkum týmu VUT v 2022: Analýza kryptografických primitiv na FPGA, bezpečnost, návrh testbedu. 2022. s. 1-18.Detail
GERLICH, T.; KANDI, A.; BAKSI, A.; MARTINÁSEK, Z.; GUILLEY, S.; GAN, P.; BREIER, J.; CHATTOPADHYAY, A.; BHASIN, S.; SHRIVASTWA, R. Hardware Implementation of ASCON. NIST, 2023. p. 1-14.Detail
JEDLIČKA, P.; MALINA, L.; SOCHA, P.; GERLICH, T.; MARTINÁSEK, Z.; HAJNÝ, J. On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography. In ARES '22: Proceedings of the 17th International Conference on Availability, Reliability and Security. Vienna, Austria: ACM, 2022. p. 1-9. ISBN: 978-1-4503-9670-7.Detail
HAJNÝ, J.; MARTINÁSEK, Z.; MALINA, L.; JEDLIČKA, P.; ŠVENDA, P.; NOVOTNÝ, M. Prezentace z Workshopu SecTools 2023. 2023.Detail
HAJNÝ, J.; MALINA, L.; MARTINÁSEK, Z.; JEDLIČKA, P.; ŠVENDA, P.; NOVOTNÝ, M.: Workshop SecTools 2023. Praha (18.09.2023)Detail