Detail publikačního výsledku

Web-Based Simulator of Superscalar RISC-V Processors

JAROŠ, J.; MAJER, M.; HORKÝ, J.; VÁVRA, J.

Originální název

Web-Based Simulator of Superscalar RISC-V Processors

Anglický název

Web-Based Simulator of Superscalar RISC-V Processors

Druh

Stať ve sborníku v databázi WoS či Scopus

Originální abstrakt

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to  grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Anglický abstrakt

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to  grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Klíčová slova

Web-based simulator, RISC-V processor, superscalar processor 

Klíčová slova v angličtině

Web-based simulator, RISC-V processor, superscalar processor 

Autoři

JAROŠ, J.; MAJER, M.; HORKÝ, J.; VÁVRA, J.

Rok RIV

2025

Vydáno

18.11.2024

Nakladatel

Institute of Electrical and Electronics Engineers

Místo

Atlanta, GA

ISBN

979-8-3503-5554-3

Kniha

Proceedings of SC 2024-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis

Strany od

1676

Strany do

1684

Strany počet

9

URL

https://ieeexplore.ieee.org/document/10820703

BibTex

@inproceedings{BUT192198,
  author="Jiří {Jaroš} and Michal {Majer} and Jakub {Horký} and Jan {Vávra}",
  title="Web-Based Simulator of Superscalar RISC-V Processors",
  booktitle="Proceedings of SC 2024-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis",
  year="2024",
  pages="1676--1684",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Atlanta, GA",
  doi="10.1109/SCW63240.2024.00209",
  isbn="979-8-3503-5554-3",
  url="https://ieeexplore.ieee.org/document/10820703"
}

Dokumenty

SC 2024
Článek