Detail publikačního výsledku

Universal Pseudo-random Generation of Assembler Codes for Processors

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z.

Originální název

Universal Pseudo-random Generation of Assembler Codes for Processors

Anglický název

Universal Pseudo-random Generation of Assembler Codes for Processors

Druh

Stať ve sborníku mimo WoS a Scopus

Originální abstrakt

The paper describes a universal generation of test stimuli  based  on  solving  constraints.  The  architecture  of  the universal generator consists of two formal models. The first one is used for describing the generated scenario and the second one for  specifying  constraints  for  this  scenario.  The  generation  of the  assembler  programs  for  Application-Specific  Instruction-set Processors (ASIPs) is an example of the use of this architecture. The  necessary  steps  needed  to  generate  a  valid  assembler  code are  described.  The  quality  of  the  generator  is  measured by  the instruction and statement coverage in functional verification.

Anglický abstrakt

The paper describes a universal generation of test stimuli  based  on  solving  constraints.  The  architecture  of  the universal generator consists of two formal models. The first one is used for describing the generated scenario and the second one for  specifying  constraints  for  this  scenario.  The  generation  of the  assembler  programs  for  Application-Specific  Instruction-set Processors (ASIPs) is an example of the use of this architecture. The  necessary  steps  needed  to  generate  a  valid  assembler  code are  described.  The  quality  of  the  generator  is  measured by  the instruction and statement coverage in functional verification.

Klíčová slova

universal generator, assembler, processor, functional verification

Klíčová slova v angličtině

universal generator, assembler, processor, functional verification

Autoři

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z.

Vydáno

01.01.2015

Nakladatel

COST, European Cooperation in Science and Technology

Místo

Grenoble

Kniha

Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale

Strany od

70

Strany do

73

Strany počet

4

URL

http://www.median-project.eu/wp-content/uploads/18_IV-2_median2015.pdf

BibTex

@inproceedings{BUT168443,
  author="Ondřej {Čekan} and Marcela {Zachariášová} and Zdeněk {Kotásek}",
  title="Universal Pseudo-random Generation of Assembler Codes for Processors",
  booktitle="Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale",
  year="2015",
  pages="70--73",
  publisher="COST, European Cooperation in Science and Technology",
  address="Grenoble",
  url="http://www.median-project.eu/wp-content/uploads/18_IV-2_median2015.pdf"
}