Detail publikace

CMOS-RC Colpitts Oscillator Design Using Floating Fractional-Order Inductance Simulator

KARTCI, A. HERENCSÁR, N. BRANČÍK, L. SALAMA, K. N.

Originální název

CMOS-RC Colpitts Oscillator Design Using Floating Fractional-Order Inductance Simulator

Anglický název

CMOS-RC Colpitts Oscillator Design Using Floating Fractional-Order Inductance Simulator

Jazyk

en

Originální abstrakt

This paper deals with CMOS fractional-order inductance (FoL) simulator design and its utilization in 2.75th-order Colpitts oscillator providing high frequency of oscillation. The proposed floating FoL is composed of two unity-gain current followers (CF +/- s), two inverting voltage buffers, a transconductor, and a fractional-order capacitor (FoC) of order 0.75, while the input intrinsic resistance of CF. is used as design parameter instead of passive resistor. The resulting equivalent inductance value of the FoL can be adjusted via order of FoC, which was emulated via 5th-order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 kHz -2.45 MHz the L. shows +/- 5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 mu m level-7 LO EPI SCN018 CMOS process parameters with +/- 1 V supply voltages.

Anglický abstrakt

This paper deals with CMOS fractional-order inductance (FoL) simulator design and its utilization in 2.75th-order Colpitts oscillator providing high frequency of oscillation. The proposed floating FoL is composed of two unity-gain current followers (CF +/- s), two inverting voltage buffers, a transconductor, and a fractional-order capacitor (FoC) of order 0.75, while the input intrinsic resistance of CF. is used as design parameter instead of passive resistor. The resulting equivalent inductance value of the FoL can be adjusted via order of FoC, which was emulated via 5th-order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 kHz -2.45 MHz the L. shows +/- 5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 mu m level-7 LO EPI SCN018 CMOS process parameters with +/- 1 V supply voltages.

Plný text v Digitální knihovně

Dokumenty

BibTex


@inproceedings{BUT149089,
  author="Aslihan {Kartci} and Norbert {Herencsár} and Lubomír {Brančík} and Khaled Nabil {Salama}",
  title="CMOS-RC Colpitts Oscillator Design Using Floating Fractional-Order Inductance Simulator",
  annote="This paper deals with CMOS fractional-order inductance (FoL) simulator design and its utilization in 2.75th-order Colpitts oscillator providing high frequency of oscillation. The proposed floating FoL is composed of two unity-gain current followers (CF +/- s), two inverting voltage buffers, a transconductor, and a fractional-order capacitor (FoC) of order 0.75, while the input intrinsic resistance of CF. is used as design parameter instead of passive resistor. The resulting equivalent inductance value of the FoL can be adjusted via order of FoC, which was emulated via 5th-order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 kHz -2.45 MHz the L. shows +/- 5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 mu m level-7 LO EPI SCN018 CMOS process parameters with +/- 1 V supply voltages.",
  address="IEEE",
  booktitle="Proceedings of the 2018 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)",
  chapter="149089",
  doi="10.1109/MWSCAS.2018.8623859",
  howpublished="electronic, physical medium",
  institution="IEEE",
  year="2018",
  month="august",
  pages="905--908",
  publisher="IEEE",
  type="conference paper"
}