Publication detail

FPGA Based 1 Gbps Ethernet Header Detector

ŠTOHANZL, M. POVALAČ, A.

Original Title

FPGA Based 1 Gbps Ethernet Header Detector

Type

conference paper

Language

English

Original Abstract

This paper presents a study about a hardware implementation of the Ethernet header detector implemented in FPGA circuits. The header detector is able to detect the TCP/IP and UDP/IP header contents for both the IPv4 and the IPv6 protocols. This hardware implementation allows access to the headers content faster than the software implementation. Therefore, it is suitable for many different high-speed Ethernet devices.

Keywords

Field Programmable Gate Array (FPGA), Ethernet, header, IP, TCP, UDP

Authors

ŠTOHANZL, M.; POVALAČ, A.

RIV year

2012

Released

29. 8. 2012

ISBN

978-80-214-4579-6

Book

Proceedings of the conference Vsacký Cáb 2012

Pages from

1

Pages to

4

Pages count

4

BibTex

@inproceedings{BUT93622,
  author="Milan {Štohanzl} and Aleš {Povalač}",
  title="FPGA Based 1 Gbps Ethernet Header Detector",
  booktitle="Proceedings of the conference Vsacký Cáb 2012",
  year="2012",
  pages="1--4",
  isbn="978-80-214-4579-6"
}