Publication detail

The Design of Hardware Checkers for Verification and Diagnostic Purposes

STRAKA, M. KOTÁSEK, Z. WINTER, J.

Original Title

The Design of Hardware Checkers for Verification and Diagnostic Purposes

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers of digital components is described. First, our experiments with PSL language and FoCs tool are demonstrated. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principles of our approach based on developing a formal language to describe the functions to be checked and a compiler which transforms the description into VHDL code are explained.

Keywords

on-line checker, on-line testing, verification, PSL, FPGA, FoCs, ModelSim

Authors

STRAKA, M.; KOTÁSEK, Z.; WINTER, J.

RIV year

2008

Released

25. 6. 2008

Publisher

The University of Technology Košice

Location

High Tatras - Stará Lesná

ISBN

978-80-8086-092-9

Book

CSE'2008 International Scientific Conference on Computer Science and Engineering

Pages from

320

Pages to

327

Pages count

7

URL

https://www.fit.vut.cz/research/publication/8646/

BibTex

@inproceedings{BUT32103,
  author="Martin {Straka} and Zdeněk {Kotásek} and Jan {Winter}",
  title="The Design of Hardware Checkers for Verification and Diagnostic Purposes",
  booktitle="CSE'2008 International Scientific Conference on Computer Science and Engineering",
  year="2008",
  pages="320--327",
  publisher="The University of Technology Košice",
  address="High Tatras - Stará Lesná",
  isbn="978-80-8086-092-9",
  url="https://www.fit.vut.cz/research/publication/8646/"
}