Publication result detail

High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA

DEDEK, T.; MAREK, T.; MARTÍNEK, T.

Original Title

High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA

English Title

High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

In this paper, we investigate three different realizations
of the same block from different points of view. The mentioned
different realizations include two realizations with
embedded processors (custom 16-bit RISC processor and
general soft-core processor) and the third realization uses
Handel-C as an example of synthesisable high-level abstraction
languages.
The results show that development time of complete
solution (HW and SW) is approximately the same for the
Handel-C design and the design with soft-core processor;
the development time of the Custom 16-bit RISC processor
is about five times higher. Moreover, the throughput of the
Handel-C design measured in the number of bits processed
in one second is the highest. The obtained frequency and
occupied area of the Handel-C design depends on the complexity
of the used program. However, results are comparable
or even better than results of the embedded processors.

English abstract

In this paper, we investigate three different realizations
of the same block from different points of view. The mentioned
different realizations include two realizations with
embedded processors (custom 16-bit RISC processor and
general soft-core processor) and the third realization uses
Handel-C as an example of synthesisable high-level abstraction
languages.
The results show that development time of complete
solution (HW and SW) is approximately the same for the
Handel-C design and the design with soft-core processor;
the development time of the Custom 16-bit RISC processor
is about five times higher. Moreover, the throughput of the
Handel-C design measured in the number of bits processed
in one second is the highest. The obtained frequency and
occupied area of the Handel-C design depends on the complexity
of the used program. However, results are comparable
or even better than results of the embedded processors.

Keywords

Internet packet processing, Embeded processors, Handel-C, FPGA

Key words in English

Internet packet processing, Embeded processors, Handel-C, FPGA

Authors

DEDEK, T.; MAREK, T.; MARTÍNEK, T.

Released

01.09.2007

Publisher

IEEE Computer Society

Location

Amsterdam

ISBN

1-4244-1060-6

Book

2007 International Conference on Field Programmable Logic and Applications

Pages from

648

Pages to

651

Pages count

4

BibTex

@inproceedings{BUT26060,
  author="Tomáš {Dedek} and Tomáš {Marek} and Tomáš {Martínek}",
  title="High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA",
  booktitle="2007 International Conference on Field Programmable Logic and Applications",
  year="2007",
  pages="648--651",
  publisher="IEEE Computer Society",
  address="Amsterdam",
  doi="10.1109/FPL.2007.4380737",
  isbn="1-4244-1060-6"
}