Publication detail

RT Level Test Optimization for Low Power Consumption

ŠKARVADA, J.

Original Title

RT Level Test Optimization for Low Power Consumption

Type

conference paper

Language

English

Original Abstract

The paper deals with low power consumption test optimization for register transfer level (RTL) circuits. A model of circuit under test (CUT), based on the theory of sets and relations is defined. In the model, the power consumption is seen as a parameter depending on circuit structure and input data used for the test. Optimization method to reduce power consumption during test application, is presented.

Keywords

Register transfer level, power consumption optimization, test vectors reordering, scan cells reordering

Authors

ŠKARVADA, J.

RIV year

2007

Released

26. 10. 2007

Publisher

Ing. Zdeněk Novotný, CSc.

Location

Brno

ISBN

978-80-7355-077-6

Book

MEMICS proceedings 2007

Pages from

185

Pages to

192

Pages count

7

BibTex

@inproceedings{BUT25354,
  author="Jaroslav {Škarvada}",
  title="RT Level Test Optimization for Low Power Consumption",
  booktitle="MEMICS proceedings 2007",
  year="2007",
  pages="185--192",
  publisher="Ing. Zdeněk Novotný, CSc.",
  address="Brno",
  isbn="978-80-7355-077-6"
}