Publication detail

State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture

SZURMAN, K. KOTÁSEK, Z.

Original Title

State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

Fault-tolerant systems implemented into SRAM-based FPGA are frequently protected by combination of triple modular redundancy and partial dynamic reconfiguration. When a part of the SRAM configuration memory with the copy of the protected circuit is reconfigured on the run, the system restart is the easiest way how to bring all three copies of the circuit back to fully synchronous and operating state. Soft core processors are complex systems which require more precise technique for synchronization of the system state space and data gained from previous calculations without disruption of processors functionality and executed program. This paper presents current state of our research focused on the state synchronization methodology for soft core processors.

Keywords

fault tolerant system, FPGA, state synchronization,  partial dynamic reconfiguration, recovery, soft core processor.

Authors

SZURMAN, K.; KOTÁSEK, Z.

Released

6. 9. 2017

Publisher

Slovak University of Technology in Bratislava

Location

Smolenice

ISBN

978-80-972784-0-3

Book

Počítačové architektúry & diagnostika 2017

Pages from

51

Pages to

54

Pages count

4

URL

https://www.fit.vut.cz/research/publication/11488/

BibTex

@inproceedings{BUT144462,
  author="Karel {Szurman} and Zdeněk {Kotásek}",
  title="State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture",
  booktitle="Počítačové architektúry & diagnostika 2017",
  year="2017",
  pages="51--54",
  publisher="Slovak University of Technology in Bratislava",
  address="Smolenice",
  isbn="978-80-972784-0-3",
  url="https://www.fit.vut.cz/research/publication/11488/"
}